@@ -420,28 +420,38 @@ static void v4_ensure_sensor_restored() {
420420}
421421
422422static struct CV610_PERI_CRG8464 peri_crg8464 ;
423+ static struct CV610_PERI_CRG8464 peri_crg8472 ;
423424static bool crg8464_changed ;
424- static void ot_ensure_sensor_enabled () {
425- // PERI_CRG8464 0x8440
426- // PERI_CRG8472 0x8460
427- struct CV610_PERI_CRG8464 crg8464 ;
428- if (mem_reg (CV610_PERI_CRG8464_ADDR , (uint32_t * )& crg8464 , OP_READ )) {
429- if (!crg8464 .sensor0_cken ) {
430- peri_crg8464 = crg8464 ;
431- // 1: clock enabled
432- crg8464 .sensor0_cken = true;
433- // 0: reset deasserted
434- crg8464 .sensor0_srst_req = false;
435- mem_reg (CV610_PERI_CRG8464_ADDR , (uint32_t * )& crg8464 , OP_WRITE );
436- crg8464_changed = true;
437- }
425+ static bool crg8472_changed ;
426+ static inline void enable_sensor_crg (uint32_t addr ,
427+ struct CV610_PERI_CRG8464 * shadow ,
428+ bool * changed ) {
429+ struct CV610_PERI_CRG8464 reg ;
430+
431+ if (!mem_reg (addr , (uint32_t * )& reg , OP_READ ))
432+ return ;
433+
434+ if (!reg .sensor0_cken || reg .sensor0_srst_req ) {
435+ * shadow = reg ; // Cache original value
436+ reg .sensor0_cken = true; // Enable clock
437+ reg .sensor0_srst_req = false; // Deassert reset
438+ mem_reg (addr , (uint32_t * )& reg , OP_WRITE );
439+ * changed = true;
438440 }
439441}
440442
443+ static void ot_ensure_sensor_enabled (void ) {
444+ enable_sensor_crg (CV610_PERI_CRG8464_ADDR , & peri_crg8464 , & crg8464_changed );
445+ enable_sensor_crg (CV610_PERI_CRG8472_ADDR , & peri_crg8472 , & crg8472_changed );
446+ }
447+
441448static void ot_ensure_sensor_restored () {
442449 if (crg8464_changed ) {
443450 mem_reg (CV610_PERI_CRG8464_ADDR , (uint32_t * )& peri_crg8464 , OP_WRITE );
444451 }
452+ if (crg8472_changed ) {
453+ mem_reg (CV610_PERI_CRG8472_ADDR , (uint32_t * )& peri_crg8472 , OP_WRITE );
454+ }
445455}
446456
447457static void hisi_hal_cleanup () {
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